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W78E365/W78E365A Data Sheet 8-BIT MICROCONTROLLER
Table of Contents1. 2. 3. 4. 5. 6. GENERAL DESCRIPTION ......................................................................................................... 3 FEATURES ................................................................................................................................. 3 PIN CONFIGURATIONS ............................................................................................................ 4 PIN DESCRIPTION..................................................................................................................... 5 BLOCK DIAGRAM ...................................................................................................................... 6 FUNCTIONAL DESCRIPTION ................................................................................................... 7 6.1 6.2 6.3 RAM ................................................................................................................................ 7 Timers 0, 1, and 2 ........................................................................................................... 8
6.2.1 6.3.1 6.3.2 Timer 2 Output .................................................................................................................8 Crystal Oscillator ..............................................................................................................8 External Clock ..................................................................................................................8 Idle Mode..........................................................................................................................8 Power-down Mode............................................................................................................9 Reduce EMI Emission ......................................................................................................9 W78E365 Special Function Registers (SFRs) and Reset Values.....................................9 Port Options Register .....................................................................................................11
Clock ............................................................................................................................... 8
6.4
Power Management........................................................................................................ 8
6.4.1 6.4.2 6.4.3
6.5 6.6
Reset............................................................................................................................... 9
6.5.1 6.6.1 6.6.2 6.6.3
Port 4 ............................................................................................................................ 10
INT2 / INT3 ...................................................................................................................11
Port 4 Base Address Registers ......................................................................................13
6.7 6.8 6.9 6.10 6.11 6.12 7. 7.1 7.2
Pulse Width Modulated Outputs (PWM)....................................................................... 15 Watchdog Timer ........................................................................................................... 18 In-System Programming (ISP) Mode............................................................................ 20
6.9.1 In-System Programming Control Register (CHPCON) ...................................................21
Software Reset ............................................................................................................. 21 H/W Reboot Mode (Boot from LDROM) ....................................................................... 22 Security ......................................................................................................................... 25 Absolute Maximum Ratings .......................................................................................... 27 D.C. Characteristics...................................................................................................... 27
ELECTRICAL CHARACTERISTICS......................................................................................... 27
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Publication Release Date: January 10, 2007 Revision A9
W78E365/W78E365A
7.3 8. 8.1 8.2 8.3 8.4 9. 9.1 9.2 10. 10.1 10.2 10.3 10.4 11. 12. 11.1 A.C. Characteristics ...................................................................................................... 29 Program Fetch Cycle .................................................................................................... 30 Data Read Cycle........................................................................................................... 31 Data Write Cycle ........................................................................................................... 32 Port Access Cycle......................................................................................................... 33 External Program Memory and Crystal ........................................................................ 34 Expanded External Data Memory and Oscillator ......................................................... 35 40-pin DIP ..................................................................................................................... 36 44-pin PLCC ................................................................................................................. 36 44-pin PQFP ................................................................................................................. 37 48-pin LQFP.................................................................................................................. 37 In-system Programming Software Examples ............................................................... 38
TIMING WAVEFORMS ............................................................................................................. 30
TYPICAL APPLICATION CIRCUIT........................................................................................... 34
PACKAGE DIMENSIONS ......................................................................................................... 36
APPLICATION NOTE ............................................................................................................... 38 REVISION HISTORY ................................................................................................................ 43
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W78E365/W78E365A
1. GENERAL DESCRIPTION
The W78E365 is an 8-bit microcontroller which has an in-system programmable Flash EPROM for firmware updating. The instruction set of the W78E365 is fully compatible with the standard 8052. The W78E365 contains a 64K bytes of main Flash APROM and a 4K bytes of auxiliary Flash LDROM which allows the contents of the 64KB main APROM to be updated by the loader program located at the LDROM; 256+1K bytes of on-chip RAM; four 8-bit bi-directional and bit-addressable I/O ports; an additional 4-bit port P4; three 16-bit timer/counters; a serial port. These peripherals are supported by a eight sources two-level interrupt capability. To facilitate programming and verification, the ROM inside the W78E365 allows the program memory to be programmed and read electronically. Once the code is confirmed, the user can protect the code for security. The W78E365 microcontroller has two power reduction modes, idle mode and power-down mode, both of which are software selectable. The idle mode turns off the processor clock but allows for continued peripheral operation. The power-down mode stops the crystal oscillator for minimum power consumption. The external clock can be stopped at any time and in any state without affecting the processor.
2. FEATURES
Fully static design 8-bit CMOS microcontroller 64K bytes of in-system programmable Flash EPROM for Application Program (APROM) 4K bytes of auxiliary ROM for Loader Program (LDROM) 256+1K bytes of on-chip RAM. (Including 1K bytes of AUX-RAM, software selectable) Four 8-bit bi-directional ports; Port 0 has internal pull-up resisters enabled by software One 4-bit multipurpose programmable port (I/O, interrupt, Chip select function) Three 16-bit timer/counters One full duplex serial port Watchdog timer 5 channel PWM Software Reset P1.0 T2 programmable clock out Eight-sources, two-level interrupt capability Built-in power management Code protection Packaged in - Lead Free (RoHS) DIP 40: - Lead Free (RoHS) PLCC 44: - Lead Free (RoHS) PQFP 44: - Lead Free (RoHS) LQFP 48: W78E365A40DL W78E365A40PL W78E365A40FL W78E365A40LL
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Publication Release Date: January 10, 2007 Revision A9
W78E365/W78E365A
3. PIN CONFIGURATIONS
40-pin DIP
T2, P1.0 T2EX, P1.1 P1.2 P1.3 P1.4 P1.5 P1.6 P1.7 RST RXD, P3.0 TXD, P3.1 INT0, P3.2 INT1, P3.3 T0, P3.4 T1, P3.5 WR, P3.6 RD, P3.7 XTAL2 XTAL1 VSS 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 22 21 VDD P0.0, AD0 P0.1, AD1 P0.2, AD2 P0.3, AD3 P0.4, AD4 P0.5, AD5 P0.6, AD6 P0.7, AD7 EA ALE PSEN P2.7, A15 P2.6, A14 P2.5, A13 P2.4, A12 P2.3, A11 P2.2, A10 P2.1, A9 P2.0, A8
44-pin PLCC
T 2 E X , PPPP 1111 .... 4321 / I N TT 23 ,, PP 1 4V ..D 0 2D A D 0 , P 0 . 0 A D 1 , P 0 . 1 A D 2 , P 0 . 2 A D 3 , P 0 . 3
P1.5 P1.6 P1.7 RST RXD, P3.0 INT2, P4.3 TXD, P3.1 INT0, P3.2 INT1, P3.3 T0, P3.4 T1, P3.5
6 5 4 3 2 1 44 43 42 41 40 7 39 38 8 37 9 36 10 35 11 34 12 33 13 32 14 31 15 30 16 29 17 18 19 20 21 22 23 24 25 26 27 28 P 3 . 6 , / W R P 3 . 7 , / R D X T A L 2 XVPP TS42 AS. . L 00 1 , A 8 P 2 . 1 , A 9 P 2 . 2 , A 1 0 P 2 . 3 , A 1 1 P 2 . 4 , A 1 2
P0.4, AD4 P0.5, AD5 P0.6, AD6 P0.7, AD7 EA P4.1 ALE PSEN P2.7, A15 P2.6, A14 P2.5, A13
44-pin PQFP
T 2 E X , PPPP 1111 .... 4321 T 2 , P 1 . 0 / I A N D T 0 3 , , P P 4V0 .D. 2D0 A D 1 , P 0 . 1 A D 2 , P 0 . 2 A D 3 , P 0 . 3
48-pin LQFP
P1.5 P1.6 P1.7 RST RXD, P3.0 INT2, P4.3 TXD, P3.1 INT0, P3.2 INT1, P3.3 T0, P3.4 T1, P3.5
1 2
44 43 42 41 40 39 38 37 36 35 34 33 32 31 3 30 4 29 5 28 6 27 7 26 8 9 25 10 24 23 11 12 13 14 15 16 17 18 19 20 21 22 P 3 . 6 , / W R P 3 . 7 , / R D X T A L 2 XVPP TS42 AS. . L 00 1 , A 8 P 2 . 1 , A 9 P 2 . 2 , A 1 0 P 2 . 3 , A 1 1 P 2 . 4 , A 1 2
P0.4, AD4 P0.5, AD5 P0.6, AD6 P0.7, AD7 EA P4.1 ALE PSEN P2.7, A15 P2.6, A14 P2.5, A13
P1.5 P1.6 P1.7 RST P3.0 P4.3 P3.1 P3.2 P3.3 P3.4 P3.5 NC
1 2 3 4 5 6 7 8 9 10 11 12
36 35 34 33 32 31 30 29 28 27 26 25
NC P0.4 P0.5 P0.6 P0.7 EA P4.1 ALE PSEN P2.7 P2.6 P2.5
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W78E365/W78E365A
4. PIN DESCRIPTION
SYMBOL TYPE DESCRIPTIONS
EA
I
EXTERNAL ACCESS ENABLE: This pin forces the processor to execute the external ROM. The ROM address and data will not be presented on the bus if the EA pin is high. PROGRAM STORE ENABLE: PSEN enables the external ROM data in the Port 0 address/data bus. When internal ROM access is performed, no PSEN strobe signal outputs originate from this pin. ADDRESS LATCH ENABLE: ALE is used to enable the address latch that separates the address from the data on Port 0. ALE runs at 1/6th of the oscillator frequency. RESET: A high on this pin for two machine cycles while the oscillator is running resets the device. CRYSTAL 1: This is the crystal oscillator input. This pin may be driven by an external clock. CRYSTAL 2: This is the crystal oscillator output. It is the inversion of XTAL1. GROUND: ground potential. POWER SUPPLY: Supply voltage for operation. PORT 0: Function is the same as that of standard 8052.
PSEN
OH
ALE RST XTAL1 XTAL2 VSS VDD P0.0 - P0.7 P1.0 - P1.7 P2.0 - P2.7 P3.0 - P3.7 P4.0 - P4.7
OH IL I O I I
I/O D This port also provides a multiplexed low order address/data bus during accesses to external memory. Port 0 has internal pull-up resisters enabled by software. I/O H PORT 1: Function is the same as that of standard 8052. PORT 2: Port 2 is a bi-directional I/O port with internal pull-ups. This port also provides the upper address bits for accesses to external memory. The P2.6 I/O H and P2.7 also provide the alternate function REBOOT which is H/W reboot from LD flash. I/O H PORT 3: Function is the same as that of the standard 8052. I/O H PORT 4: A bi-directional I/O. The P4.3 also provides the alternate function REBOOT which is H/W reboot from LD flash.
* Note: TYPE I: input, O: output, I/O: bi-directional, H: pull-high, L: pull-low, D: open drain
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Publication Release Date: January 10, 2007 Revision A9
W78E365/W78E365A
5. BLOCK DIAGRAM
P1.0
Port 1 Port 1 Latch ACC Interrupt T1 Timer 2 Timer 0 Timer 1 UART PSW ALU Stack Pointer T2
P1.7 B
Port 0 Latch Port 0
P0.0
P0.7
DPTR Temp Reg. PC
Incrementor
Addr. Reg.
P3.0
Port 3 Port 3 Latch Instruction Decoder & Sequencer SFR RAM Address 64KB Flash APROM 4KB Flash LDROM
P3.7
256+1K bytes RAM & SFR
P2.0
Port 2 Latch Port 2
Bus & Clock Controller
P2.7
P4.0 P4.3
Port 4
Port 4 Latch
Oscillator
Reset Block
Power control
XTAL1
XTAL2
ALE PSEN
RST
VCC
Vss
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W78E365/W78E365A
6. FUNCTIONAL DESCRIPTION
The W78E365 architecture consists of a core controller surrounded by various registers, four general purpose I/O ports, one special purpose programmable 4-bits I/O port, 256+1K bytes of RAM, three timer/counters, a serial port. The processor supports 111 different opcodes and references both a 64K program address space and a 64K data storage space.
6.1
RAM
The internal data RAM in the W78E365 is 256+1K bytes. It is divided into two banks: 256 bytes of scratchpad RAM and 1K bytes of AUX-RAM. These RAMs are addressed by different ways. RAM 0H - 7FH can be addressed directly and indirectly as the same as in 8051. Address pointers are R0 and R1 of the selected register bank. RAM 80H - FFH can only be addressed indirectly as the same as in 8051. Address pointers are R0, R1 of the selected registers bank. AUX-RAM 0H - 3FFH is addressed indirectly as the same way to access external data memory with the MOVX instruction. Address pointer are R0 and R1 of the selected register bank and DPTR register. An access to external data memory locations higher than 3FFH will be performed with the MOVX instruction in the same way as in the 8051. The AUX-RAM is enable after a reset. Setting the bit 4 in CHPCON register will enable the access to AUX-RAM. When executing from internal program memory, an access to AUX-RAM will not affect the Ports P0, P2, WR and RD . Example: CHPENR CHPCON XRAMAH MOV MOV ORL MOV MOV MOV MOV MOVX MOV MOV MOVX MOV MOV MOVX MOV MOVX REG REG REG F6H BFH A1H
CHPENR, #87H CHPENR, #59H CHPCON, #00010000B CHPENR, #00H XRAMAH, #01H R0, #23H A, #55H @R0, A XRAMAH, #02H R1, #FFH A, @R1 DPTR, #0134H A, #78H @DPTR, A DPTR, #7FFFH A, @DPRT
; enable AUX-RAM ; internal high address
; Write 55h data to 0123h AUX-RAM address. ; Read data from 02FFh AUX-RAM address.
; Write 78h data to 0134h AUX-RAM address. ; Read data from the external 7FFFh address SRAM Publication Release Date: January 10, 2007 Revision A9
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W78E365/W78E365A
6.2 Timers 0, 1, and 2
Timers 0, 1, and 2 each consist of two 8-bit data registers. These are called TL0 and TH0 for Timer 0, TL1 and TH1 for Timer 1, and TL2 and TH2 for Timer 2. The TCON and TMOD registers provide control functions for timers 0, 1. The T2CON register provides control functions for Timer 2. RCAP2H and RCAP2L are used as reload/capture registers for Timer 2. The operations of Timer 0 and Timer 1 are the same as in the W78C51. Timer 2 is a 16-bit timer/counter that is configured and controlled by the T2CON register. Like Timers 0 and 1, Timer 2 can operate as either an external event counter or as an internal timer, depending on the setting of bit C/T2 in T2CON. Timer 2 has three operating modes: capture, auto-reload, and baud rate generator. The clock speed at capture or auto-reload mode is the same as that of Timers 0 and 1.
6.2.1
Timer 2 Output
If set T2OE (T2MOD.1) bit and clear C/T2 (T2CON.1) bit at auto-reload mode, P1.0 will be toggled once overflow. TIMER 2 Mode Bit: 7 6 5 4 3 2 1 T2OE Mnemonic: T2MOD Address: C9H T2OE: Enable this bit to toggle P1.0 pin while Timer2 has been overflowed. 0
6.3
Clock
The W78E365 is designed with either a crystal oscillator or an external clock. Internally, the clock is divided by two before it is used by default. This makes the W78E365 relatively insensitive to duty cycle variations in the clock.
6.3.1
Crystal Oscillator
The W78E365 incorporates a built-in crystal oscillator. To make the oscillator work, a crystal must be connected across pins XTAL1 and XTAL2. In addition, a load capacitor must be connected from each pin to ground.
6.3.2
External Clock
An external clock should be connected to pin XTAL1. Pin XTAL2 should be left unconnected. The XTAL1 input is a CMOS-type input, as required by the crystal oscillator.
6.4
6.4.1
Power Management
Idle Mode
Setting the IDL bit in the PCON register enters the idle mode. In the idle mode, the internal clock to the processor is stopped. The peripherals and the interrupt logic continue to be clocked. The processor will exit idle mode when either an interrupt or a reset occurs.
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W78E365/W78E365A
6.4.2 Power-down Mode
When the PD bit in the PCON register is set, the processor enters the power-down mode. In this mode all of the clocks are stopped, including the oscillator. To exit from power-down mode is by a hardware reset or external interrupts INT0 to INT1 when enabled and set to level triggered.
6.4.3
Reduce EMI Emission
The W78E365 allows user to diminish the gain of on-chip oscillator amplifier by using programmer to clear the B7 bit of security register. Once B7 is set to 0, a half of gain will be decreased. Care must be taken if user attempts to diminish the gain of oscillator amplifier, reducing a half of gain may affect the external crystal operating improperly at high frequency. The value of C1 and C2 may need some adjustment while running at lower gain. ALE Off Function Auxiliary Register Bit: 7 6 5 4 3 2 1 0 ALEOFF
Mnemonic: AUXR ALEOFF: Set this bit to disable ALE output.
Address: 8EH
6.5
Reset
The external RESET signal is sampled at S5P2. To take effect, it must be held high for at least two machine cycles while the oscillator is running. An internal trigger circuit in the reset line is used to deglitch the reset line when the W78E365 is used with an external RC network. The reset logic also has a special glitch removal circuit that ignores glitches on the reset line. During reset, the ports are initialized to FFH, the stack pointer to 07H, PCON (with the exception of bit 4) to 00H, and all of the other SFR registers except SBUF to 00H. SBUF is not reset.
6.5.1
F8 F0 E8 E0 D8 D0 C8 C0
W78E365 Special Function Registers (SFRs) and Reset Values
+B 00000000
CHPENR 00000000
+ACC 00000000 +P4 11111111 +PSW 00000000 +T2CON 00000000 +XICON 00000000 T2MOD 00000000 RCAP2L 00000000 P4CONA 00000000 RCAP2H 00000000 P4CONB 00000000 TL2 00000000 SFRAL 00000000 TH2 00000000 SFRAH 00000000 PWMCON2 00000000 SFRFD 00000000 PWM4 00000000 SFRCN 00000000 PWMP 00000000 PWM0 00000000 PWM1 00000000 PWMCON1 00000000 PWM2 00000000 PWM3 00000000
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Publication Release Date: January 10, 2007 Revision A9
W78E365/W78E365A
W78E365 Special Function Registers (SFRs) and Reset Values, continued
B8 B0 A8 A0 98 90 88 80
Notes:
+IP 00000000 +P3 00000000 +IE 00000000 +P2 11111111 +SCON 00000000 +P1 11111111 +TCON 00000000 +P0 11111111 TMOD 00000000 SP 00000111 TL0 00000000 DPL 00000000 TL1 00000000 DPH 00000000 XRAMAH 00000000 SBUF xxxxxxxx P41AL 00000000 TH0 00000000 P40AL 00000000 P41AH 00000000 TH1 00000000 P40AH 00000000 AUXR 00000000 POR 00000000 P43AL 00000000 P42AL 00000000 P43AH 00000000 P42AH 00000000 P4CSIN 00000000
CHPCON 0xx00000
WDTC 00000000 PCON 00110000
1. The SFRs marked with a plus sign(+) are both byte- and bit-addressable. 2. The text of SFR with bold type characters are extension function registers.
6.6
Port 4
Port 4, address D8H, is a 8-bit multipurpose programmable I/O port. Each bit can be configured individually by software. The Port 4 has four different operation modes. Mode 0: P4.0-P4.3 is a bi-directional I/O port which is same as port 1. P4.2 and P4.3 also serve as external interrupt PSEN and INT2 if enabled. Mode 1: P4.0-P4.3 are read strobe signals that are synchronized with RD signal at specified addresses. These signals can be used as chip-select signals for external peripherals. Mode 2: P4.0-P4.3 are write strobe signals that are synchronized with WR signal at specified addresses. These signals can be used as chip-select signals for external peripherals. Mode 3: P4.0-P4.3 are read/write strobe signals that are synchronized with RD or WR signal at specified addresses. These signals can be used as chip-select signals for external peripherals. When Port 4 is configured with the feature of chip-select signals, the chip-select signal address range depends on the contents of the SFR P4xAH, P4xAL, P4CONA and P4CONB. The registers P4xAH and P4xAL contain the 16-bit base address of P4.x. The registers P4CONA and P4CONB contain the control bits to configure the Port 4 operation mode.
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W78E365/W78E365A
6.6.1 Port Options Register
Bit: 7 6 5 4 3 2 1 0 P0UP
Mnemonic: POR
Address: 86H
P0UP: Enable Port 0 weak up. The pins of Port 0 can be configured with either the open drain or standard port with internal pull-up. By the default, Port 0 is an open drain bi-directional I/O port. When the P0UP bit in the POR register is set, the pins of port 0 will perform a bi-directional I/O port with internal pull-up that is structurally the same Port2.
6.6.2
INT2 /INT3
Two additional external interrupts, INT2 and INT3 , whose functions are similar to those of external interrupt 0 and 1 in the standard 80C52. The functions/status of these interrupts are determined/shown by the bits in the XICON (External Interrupt Control) register. The XICON register is bit-addressable but is not a standard register in the standard 80C52. Its address is at 0C0H. To set/clear bits in the XICON register, one can use the "SETB ( CLR ) bit" instruction. For example, "SETB 0C2H" sets the EX2 bit of XICON. XICON - external interrupt control (C0H) PX3 EX3 IE3 IT3 PX2 EX2 IE2 IT2
PX3: External interrupt 3 priority high if set EX3: External interrupt 3 enable if set IE3: If IT3 = 1, IE3 is set/cleared automatically by hardware when interrupt is detected/serviced IT3: External interrupt 3 is falling-edge/low-level triggered when this bit is set/cleared by software PX2: External interrupt 2 priority high if set EX2: External interrupt 2 enable if set IE2: If IT2 = 1, IE2 is set/cleared automatically by hardware when interrupt is detected/serviced IT2: External interrupt 2 is falling-edge/low-level triggered when this bit is set/cleared by software
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Publication Release Date: January 10, 2007 Revision A9
W78E365/W78E365A
Eight-source interrupt information:
INTERRUPT SOURCE VECTOR ADDRESS POLLING SEQUENCE WITHIN PRIORITY LEVEL ENABLE REQUIRED SETTINGS INTERRUPT TYPE EDGE/LEVEL
External Interrupt 0 Timer/Counter 0 External Interrupt 1 Timer/Counter 1 Serial Port Timer/Counter 2 External Interrupt 2 External Interrupt 3
03H 0BH 13H 1BH 23H 2BH 33H 3BH
0 (highest) 1 2 3 4 5 6 7 (lowest)
IE.0 IE.1 IE.2 IE.3 IE.4 IE.5 XICON.2 XICON.6
TCON.0 TCON.2 XICON.0 XICON.3
P4CONB (C3H)
BIT NAME FUNCTION
00: Mode 0. P4.3 is a general purpose I/O port which is the same as Port1. 01: Mode 1. P4.3 is a Read Strobe signal for chip select purpose. The address range depends on the SFR P43AH, P43AL, P43CMP1 and P43CMP0. 7, 6 P43FUN1 10: Mode 2. P4.3 is a Write Strobe signal for chip select purpose. The address P43FUN0 range depends on the SFR P43AH, P43AL, P43CMP1 and P43CMP0. 11: Mode 3. P4.3 is a Read/Write Strobe signal for chip select purpose. The address range depends on the SFR P43AH, P43AL, P43CMP1, and P43CMP0. Chip-select signals address comparison: 00: Compare the full address (16 bits length) with the base address register P43AH, P43AL. 01: Compare the 15 high bits (A15-A1) of address bus with the base address P43CMP1 register P43AH, P43AL. P43CMP0 10: Compare the 14 high bits (A15-A2) of address bus with the base address register P43AH, P43AL. 11: Compare the 8 high bits (A15-A8) of address bus with the base address register P43AH, P43AL. P42FUN1 The P4.2 function control bits which are the similar definition as P43FUN1, P42FUN0 P43FUN0. P42CMP1 The P4.2 address comparator length control bits which are the similar definition P42CMP0 as P43CMP1, P43CMP0.
5, 4
3, 2 1, 0
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W78E365/W78E365A
P4CONA (C2H)
BIT NAME FUNCTION
7, 6 5, 4 3, 2 1, 0
P41FUN1 The P4.1 function control bits which are the similar definition as P43FUN1, P41FUN0 P43FUN0. P41CMP1 The P4.1 address comparator length control bits which are the similar definition P41CMP0 as P43CMP1, P43CMP0. P40FUN1 The P4.0 function control bits which are the similar definition as P43FUN1, P40FUN0 P43FUN0. P40CMP1 The P4.0 address comparator length control bits which are the similar definition P40CMP0 as P43CMP1, P43CMP0.
P4CSIN (AEH)
BIT NAME FUNCTION
7
The active polarity of P4.3 when pin P4.3 is defined as read and/or write strobe signal. = 1: P4.3 is active high when pin P4.3 is defined as read and/or write strobe P43CSINV signal. = 0: P4.3 is active low when pin P4.3 is defined as read and/or write strobe signal. P42CSINV The similarity definition as P43SINV. P41CSINV The similarity definition as P43SINV. P40CSINV The similarity definition as P43SINV. Reserve Reserve 0 0
6 5 4 3 2 1 0
6.6.3
Port 4 Base Address Registers
P40AH contains the high-order byte of address,
P40AH, P40AL: The Base address register for comparator of P4.0. P40AL contains the low-order byte of address. P41AH, P41AL: The Base address register for comparator of P4.1. P41AL contains the low-order byte of address. P42AH, P42AL: The Base address register for comparator of P4.2. P42AL contains the low-order byte of address. P43AH, P43AL: The Base address register for comparator of P4.3. P43AL contains the low-order byte of address.
P41AH contains the high-order byte of address,
P42AH contains the high-order byte of address,
P43AH contains the high-order byte of address,
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Publication Release Date: January 10, 2007 Revision A9
W78E365/W78E365A
P4 (D8H)
BIT NAME FUNCTION
7 6 5 4 3 2 1 0
P47 P46 P45 P44 P43 P42 P41 P40
I/O pin I/O pin. I/O pin. I/O pin. Port 4 Data bit which outputs to pin P4.3 at mode 0. Port 4 Data bit. which outputs to pin P4.2 at mode 0. Port 4 Data bit. which outputs to pin P4.1at mode 0. Port 4 Data bit which outputs to pin P4.0 at mode 0.
Here is an example to program the P4.0 as a write strobe signal at the I/O port address 1234H - 1237H and positive polarity, and P4.1 - P4.3 are used as general I/O ports. MOV MOV MOV MOV MOV P40AH, #12H P40AL, #34H P4CONA, #00001010B P4CONB, #00H P2ECON, #10H ; Base I/O address 1234H for P4.0 ; P4.0 a write strobe signal and address line A0 and A1 are masked. ; P4.1 - P4.3 as general I/O port which are the same as PORT1 ; Write the P40SINV = 1 to inverse the P4.0 write strobe polarity ; default is negative.
Then any instruction MOVX @DPTR, A (with DPTR = 1234H - 1237H) will generate the positive polarity write strobe signal at pin P4.0. And the instruction MOV P4, #XX will output the bit3 to bit1 of data #XX to pin P4.3 - P4.1.
P4xCSINV P4 REGISTER P4.x DATA I/O RD_CS MUX 4->1 WR_CS READ WRITE
RD/WR_CS PIN P4.x
ADDRESS BUS EQUAL REGISTER P4xAL P4xAH
P4xFUN0 P4xFUN1
Bit Length Selectable comparator REGISTER P4xCMP0 P4xCMP1
P4.x INPUT DATA BUS
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W78E365/W78E365A
6.7 Pulse Width Modulated Outputs (PWM)
There are five pulse width modulated output channels to generate pulses of programmable length and interval. The repetition frequency is defined by an 8-bit prescaler PWMP, which supplies the clock for the counter. The prescaler and counter are common to both PWM channels. The 8-bit counter counts modular 255 (0 ~ 254). The value of the 8-bit counter compared to the contents of five registers: PWM0, PWM1, PWM2, PWM3 and PWM4. Provided the contents of either these registers is greater than the counter value, the corresponding PWM0, PWM1, PWM2, PWM3 or PWM4 output is set HIGH. If the contents of these registers are equal to, or less than the counter value, the output will be LOW. The pulse-width-ratio is defined by the contents of the registers PWM0, PWM1, PWM2, PWM3 and PWM4. The pulse-width-ratio is in the range of 0 to 1 and may be programmed in increments of 1/255. ENPWM0, ENPWM1, ENPWM2, ENPWM3 and ENPWM4 bit will enable or disable PWM output. Buffered PWM outputs may be used to drive DC motors. The rotation speed of the motor would be proportional to the contents of PWM0/1/2/3/4. The repetition frequency fpwm , at the PWM0/1/2/3/4 output is given by:
fpwm =
fosc 2 x (1 + PWMP) x 255
Prescaler division factor = PWM + 1 PWMn high/low ratio of PWMn =
(PWMn) 255 - (PWMn)
This gives a repetition frequency range of 123 Hz to 31.4K Hz ( fosc = 16M Hz). By loading the PWM registers with either 00H or FFH, the PWM channels will output a constant HIGH or LOW level, respectively. Since the 8-bit counter counts modulo 255, it can never actually reach the value of the PWM registers when they are loaded with FFH. When a compare register (PWM0, PWM1, PWM2, PWM3, PWM4) is loaded with a new value, the associated output updated immediately. It does not have to wait until the end of the current counter period. There is weakly pulled high on PWM output.
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Publication Release Date: January 10, 2007 Revision A9
W78E365/W78E365A
ENPWM 0/1/2/3/4/5
PWM0 Register
PWM0 Counter
X + Y X + Y X Y > PWM1OE PWM1 (P1.4)
1/2 Fosc
PWMP Counter
> -PWM0OE
8-bits Counter
PWM0 (P1.3)
PWM1 Register
PWM1 Counter
PWM2 Register
PWM2 Counter
+ > PWM2OE PWM2 (P1.5)
PWM3 Register
PWM3 Counter
X Y
+ > PWM3OE PWM3 (P1.6)
PWM4 Register
PWM4 Counter
X Y
+ > PWM4OE PWM4 (P1.7)
FIGURE 1 PWM DIAGRAM
Please refer as below code. mov pwmcon1, #00110011b mov pwmcon2, #00000101b mov pwmp, #40h jb p1.3, $ mov pwm0, #14h jb p1.4, $ mov pwm1, #18h jb p1.5, $ mov pwm2, #20h jb p1.6, $ mov pwm3, #b0h jb p1.7,$ mov pwm4, #40h mov pwmcon1, #11111111b ; enable pwm3, 2, 1, 0 ; enable pwm4 ; Fpwm = XT/(2*(1+pwmp)*255) ; duty cycle high/low = pwm0/(255-pmw0)
; output enable pwm3, 2, 1, 0
- 16 -
W78E365/W78E365A
PWM3 Register Bit: 7 6 5 4 3 2 1 0
Mnemonic: PWM3 PWM2 Register Bit: 7 6 5 4
Address: DEH
3
2
1
0
Mnemonic: PWM2 PWM Control 1 Register Bit: 7
PWM3OE
Address: DDH
6
PWM2OE
5
ENPWM3
4
ENPWM2
3
PWM1OE
2
PWM0OE
1
ENPWM1
0
ENWPM0
Mnemonic: PWMCON1 PWM3OE: Output enable for PWM3 PWM2OE: Output enable for PWM2 ENPWM3: Enable PWM3 ENPWM2: Enable PWM2 PWM1OE: Output enable for PWM1 PWM0OE: Output enable for PWM0 ENPWM1: Enable PWM1 ENPWM0: Enable PWM0 PWM1 Register Bit: 7 6 5 4
Address: DCH
3
2
1
0
Mnemonic: PWM1 PWM0 Register Bit: 7 6 5 4
Address: DBH
3
2
1
0
Mnemonic: PWM0 PWMP Register Bit: 7 6 5 4
Address: DAH
3
2
1
0
Mnemonic: PWMP
Address: D9H
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Publication Release Date: January 10, 2007 Revision A9
W78E365/W78E365A
PWM4 Register Bit: 7 6 5 4 3 2 1 0
Mnemonic: PWM4 PWM Control 2 Register Bit: 7 6 5 4 -
Address: CFH
3 -
2 PWM4OE Address: CEH
1 -
0 ENWPM4
Mnemonic: PWMCON2 PWM4OE: Output enable for PWM4 ENPWM: Enable for PWM4
6.8
Watchdog Timer
The Watchdog timer is a free-running timer which can be programmed by the user to serve as a system monitor, a time-base generator or an event timer. It is basically a set of dividers that divide the system clock. The divider output is selectable and determines the time-out interval. When the time-out occurs, a system reset can also be caused if it is enabled. The main use of the Watchdog timer is as a system monitor. This is important in real-time control applications. In case of power glitches or electromagnetic interference, the processor may begin to execute errant code. If this is left unchecked the entire system may crash. The watchdog time-out selection will result in different time-out values depending on the clock speed. The Watchdog timer will de disabled on reset. In general, software should restart the Watchdog timer to put it into a known state. The control bits that support the Watchdog timer are discussed below. Watchdog Timer Control Register Bit: 7 ENW 6 CLRW 5 WIDL 4 3 2 PS2 1 PS1 0 PS0
Mnemonic: WDTC
Address: 8FH
ENW : Enable watch-dog if set. CLRW : Clear watch-dog timer and prescaler if set. This flag will be cleared automatically WIDL : If this bit is set, watch-dog is enabled under IDLE mode. If cleared, watch-dog is disabled under IDLE mode. Default is cleared.
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W78E365/W78E365A
PS2, PS1, PS0: Watch-dog prescaler timer select. Prescaler is selected when set PS2-0 as follows:
PS2 PS1 PS0 PRESCALER SELECT
0 0 0 0 1 1 1 1
0 0 1 1 0 0 1 1
0 1 0 1 0 1 0 1
2 4 8 16 32 64 128 256
The time-out period is obtained using the following equation:
1 x 214 x PRESCALER x 1000 x 12 mS OSC
Before Watchdog time-out occurs, the program must clear the 14-bit timer by writing 1 to WDTC.6 (CLRW). After 1 is written to this bit, the 14-bit timer, prescaler and this bit will be reset on the next instruction cycle. The Watchdog timer is cleared on reset.
ENW
WIDL IDLE
EXTERNAL RESET 14-BIT TIMER
CLEAR
OSC
1/12
PRESCALER
INTERNAL RESET
Watchdog Timer Block Diagram
CLRW
Typical Watch-Dog time-out period when OSC = 20 MHz
PS2 PS1 PS0 WATCHDOG TIME-OUT PERIOD
0 0 0 0 1 1 1 1
0 0 1 1 0 0 1 1
0 1 0 1 0 1 0 1
19.66 mS 39.32 mS 78.64 mS 157.28 mS 314.57 mS 629.14 mS 1.25 S 2.50 S
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Publication Release Date: January 10, 2007 Revision A9
W78E365/W78E365A
6.9 In-System Programming (ISP) Mode
The W78E365 equips one 64K byte of main ROM bank for application program (called APROM) and one 4K byte of auxiliary ROM bank for loader program (called LDROM). In the normal operation, the microcontroller executes the code in the APROM. If the content of APROM needs to be modified, the W78E365 allows user to activate the In-System Programming (ISP) mode by setting the CHPCON register. The CHPCON is read-only by default, software must write two specific values 87H, then 59H sequentially to the CHPENR register to enable the CHPCON write attribute. Writing CHPENR register with the values except 87H and 59H will close CHPCON register write attribute. The W78E365 achieves all in-system programming operations including enter/exit ISP Mode, program, erase, read ... etc, during device in the idle mode. Setting the bit CHPCON.0 the device will enter in-system programming mode after a wake-up from idle mode. Because device needs proper time to complete the ISP operations before awaken from idle mode, software may use timer interrupt to control the duration for device wake-up from idle mode. To perform ISP operation for revising contents of APROM, software located at APROM setting the CHPCON register then enter idle mode, after awaken from idle mode the device executes the corresponding interrupt service routine in LDROM. Because the device will clear the program counter while switching from APROM to LDROM, the first execution of RETI instruction in interrupt service routine will jump to 00H at LDROM area. The device offers a software reset for switching back to APROM while the content of APROM has been updated completely. Setting CHPCON register bit 0, 1 and 7 to logic-1 will result a software reset to reset the CPU. The software reset serves as a external reset. This in-system programming feature makes the job easy and efficient in which the application needs to update firmware frequently. In some applications, the in-system programming feature make it possible to easily update the system firmware without opening the chassis.
SFRAH, SFRAL: The objective address of on-chip ROM in the in-system programming mode.
SFRAH contains the high-order byte of address, SFRAL contains the low-order byte of address.
SFRFD: The programming data for on-chip ROM in programming mode. SFRCN: The control byte of on-chip ROM programming mode. SFRCN (C7)
BIT NAME FUNCTION
7 6 5 4 3, 2, 1, 0
WFWIN OEN CEN CTRL[3:0]
Reserve. On-chip ROM bank select for in-system programming. = 0: 64K bytes ROM bank is selected as destination for re-programming. = 1: 4K bytes ROM bank is selected as destination for re-programming. ROM output enable. ROM chip enable. The flash control signals
- 20 -
W78E365/W78E365A
MODE
WFWIN
CTRL<3:0>
OEN
CEN
SFRAH, SFRAL
SFRFD
Erase 64KB APROM Program 64KB APROM Read 64KB APROM Erase 4KB LDROM Program 4KB LDROM Read 4KB LDROM
0 0 0 1 1 1
0010 0001 0000 0010 0001 0000
1 1 0 1 1 0
0 0 0 0 0 0
X Address in Address in X Address in Address in
X Data in Data out X Data in Data out
6.9.1
In-System Programming Control Register (CHPCON)
CHPCON (BFH)
BIT NAME FUNCTION
7 6 5 4 3 2 1 0
SWRESET LD/AP ENAUXRAM 1 FBOOTSL FPROGEN
When this bit is set to 1, and both FBOOTSL and FPROGEN are set to 1. It will enforce microcontroller reset to initial condition just like power on reset. Reserve. This bit is read only. 1: CPU is running LDROM program. 0: CPU is running APROM program. 1: Enable on-chip AUX-RAM. 0: Disable the on-chip AUX-RAM Must be 1 Reserve. When this bit is set to 1, and both SWRESET and FPROGEN are set to 1. It will enforce microcontroller reset to initial condition just like power on reset. When this bit is set to 1, and both SWRESET and FBOOTSL are set to 1. It will enforce microcontroller reset to initial condition just like power on reset.
This register is protected by CHPENR register. Please write as below procedures while you would like to write CHPCON register. Mov CHPENR, #87h Mov CHPENR, #59h Anl CHPCON, #EFh ; Disable AUX-RAM Mov CHPENR, #0h
6.10 Software Reset
Set CHPCON = 0X83, timer and enter IDLE mode. CPU will reset and restart from APFLASH after time out.
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Publication Release Date: January 10, 2007 Revision A9
W78E365/W78E365A
6.11 H/W Reboot Mode (Boot from LDROM)
By default, the W78E365 boots from APROM program after a power on reset. On some occasions, user can force the W78E365 to boot from the LDROM program via following settings. The possible situation that you need to enter H/W REBOOT mode when the APROM program can not run properly and device can not jump back to LDROM to execute in-system programming function. Then you can use this H/W REBOOT mode to force the W78E365 jumps to LDROM and executes in-system programming procedure. When you design your system, you may reserve the pins P2.6, P2.7 to switches or jumpers. For example in a CD-ROM system, you can connect the P2.6 and P2.7 to PLAY and EJECT buttons on the panel. When the APROM program fails to execute the normal application program. User can press both two buttons at the same time and then turn on the power of the personal computer to force the W78E365 to enter the H/W REBOOT mode. After power on of personal computer, you can release both buttons and finish the in-system programming procedure to update the APROM code. In application system design, user must take care of the P2, P3, ALE, EA and PSEN pin value at reset to prevent from accidentally activating the programming mode or H/W REBOOT mode. It is necessary to add 10K resistor on these P2.6, P2.7 and P4.3 pins. H/W Reboot Mode
P4.3 P2.7 P2.6 MODE
X L
L X
L X
REBOOT REBOOT
The Reset Timing For Entering F04KBOOT Mode
P2.7
Hi-Z
P2.6
Hi-Z
RST
30 mS 10 mS
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W78E365/W78E365A
The Algorithm of In-System Programming
Part 1:32KB APROM START
procedure of entering In-System Programming Mode
Enter In-System Programming Mode ? (conditions depend on user's application) Yes
No
Setting control registers MOV CHPENR,#87H MOV CHPENR,#59H MOV CHPCON,#03H
Execute the normal application program
Setting Timer (about 1.5 us) and enable timer interrupt
END
Start Timer and enter idle Mode. (CPU will be wakened from idle mode by timer interrupt, then enter In-System Programming mode)
CPU will be wakened by interrupt and re-boot from 4KB LDROM to execute the loader program.
Go
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Publication Release Date: January 10, 2007 Revision A9
W78E365/W78E365A
Part 2: 4KB LDROM
Go Procedure of Updating the 32KB APROM
Timer Interrupt Service Routine: Stop Timer & disable interrupt PGM
Yes Is F04KBOOT Mode? (CHPCON.7=1) No Reset the CHPCON Register: MOV CHPENR,#87H MOV CHPENR,#59H MOV CHPCON,#03H Setting Timer and enable Timer interrupt for wake-up . (50us for program operation) End of Programming ?
Yes
No
Is currently in the F04KBOOT Mode ? No Software reset CPU and re-boot from the 32KB APROM. MOV CHPENR,#87H MOV CHPENR,#59H MOV CHPCON,#83H
Yes
Get the parameters of new code
Setting Timer and enable Timer interrupt for wake-up . (15 ms for erasing operation) (Address and data bytes) through I/O ports, UART or other interfaces.
Setting erase operation mode: MOV SFRCN,#22H (Erase 32KB APROM)
Setting control registers for programming: MOV SFRAH,#ADDRESS_H MOV SFRAL,#ADDRESS_L MOV SFRFD,#DATA MOV SFRCN,#21H
Start Timer and enter IDLE Mode. (Erasing...)
Hardware Reset to re-boot from new 32 KB APROM. (S/W reset is invalid in F04KBOOT Mode)
End of erase operation. CPU will be wakened by Timer interrupt.
END
Executing new code from address 00H in the 32KB APROM.
PGM
- 24 -
W78E365/W78E365A
6.12 Security
During the on-chip ROM programming mode, the ROM can be programmed and verified repeatedly. Until the code inside the ROM is confirmed OK, the code can be protected. The protection of ROM and those operations on it are described below. The W78E365 has a Security Register that can be accessed in programming mode. Those bits of the Security Registers can not be changed once they have been programmed from high to low. They can only be reset through erase-all operation. The Security Register is located at the 0FFFFH of the LDROM space.
B7 Reserved
B2 B1 B0
Security Bits
4KB On-chip ROM Program Memory LDROM
0000h 32KB On-chip ROM Program Memory 0FFFh APROM
B0: Lock bit, logic 0: active B1: MOVC inhibit, logic 0: the MOVC instruction in external memory cannot access the code in internal memory. logic 1: no restriction. B2: Encryption logic 0: the encryption logic enable logic 1: the encryption logic disable B07: Osillator Control logic 0: 1/2 gain logic 1: Full gain Default 1 for all security bits. Reserved bits must be kept in logic 1.
Reserved Reserved
7FFFh
Security Register
FFFFh
Special Setting Register
Lock bit This bit is used to protect the customer's program code in the W78E365. It may be set after the programmer finishes the programming and verifies sequence. Once this bit is set to logic 0, both the ROM data and Security Register can not be accessed again. MOVC Inhibit This bit is used to restrict the accessible region of the MOVC instruction. It can prevent the MOVC instruction in external program memory from reading the internal program code. When this bit is set to logic 0, a MOVC instruction in external program memory space will be able to access code only in the external memory, not in the internal memory. A MOVC instruction in internal program memory space will always be able to access the ROM data in both internal and external memory. If this bit is logic 1, there are no restrictions on the MOVC instruction.
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Publication Release Date: January 10, 2007 Revision A9
W78E365/W78E365A
Encryption This bit is used to enable/disable the encryption logic for code protection. Once encryption feature is enabled, the data presented on port 0 will be encoded via encryption logic. Only whole chip erase will reset this bit. Oscillator Control W78E365/E516 allow user to diminish the gain of on-chip oscillator amplifier by using programmer to set the bit B7 of security register. Once B7 is set to 0, a half of gain will be decreased. Care must be taken if user attempts to diminish the gain of oscillator amplifier, reducing a half of gain may improperly affect the external crystal operation at high frequency above 24 MHz. The value of R and C1, C2 may need some adjustment while running at lower gain.
- 26 -
W78E365/W78E365A
7. ELECTRICAL CHARACTERISTICS
7.1 Absolute Maximum Ratings
PARAMETER SYMBOL MIN. MAX. UNIT
DC Power Supply Input Voltage Operating Temperature Storage Temperature
VDD-VSS VIN TA TST
-0.3 VSS -0.3 0 -55
+6.0 VDD +0.3 70 +150
V V C C
Note: Exposure to conditions beyond those listed under Absolute Maximum Ratings may adversely affect the life and reliability of the device.
7.2
D.C. Characteristics
SPECIFICATION MIN. MAX. UNIT
(VDD - VSS= 5V 10%, TA = 25C, Fosc = 20 MHz, unless otherwise specified.)
SYMBOL
PARAMETER
TEST CONDITIONS
VDD IDD IIDLE IPWDN IIN1 IIN2 ILK ITL[*4] VIL1 V IL2
Operating Voltage Operating Current Idle Current Power Down Current Input Current P1, P2, P3, P4 Input Current RST Input Leakage Current
4.5 -50 -10 -10
5.5 20 6 10
V mA mA A A A A A V V
RST = 1, P0 = VDD No load VDD = 5.5V Idle mode VDD = 5.5V Power-down mode VDD = 5.5V VDD = 5.5V VIN = 0V or VDD VDD = 5.5V 0+10 +300 +10 -200 0.8 0.8
P0, EA Logic 1 to 0 Transition Current P1, P2, P3, P4 Input Low Voltage P0, P1, P2, P3, P4, EA Input Low Voltage RST 0 0 -500
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Publication Release Date: January 10, 2007 Revision A9
W78E365/W78E365A
D.C. Characteristics, continued
SYMBOL
PARAMETER MIN.
SPECIFICATION MAX. UNIT
TEST CONDITIONS
V IL3 VIH1 VIH2 VIH3 VOL1 VOL2 Isk1 Isk2 VOH1 VOH2 Isr1 Isr2
Notes:
Input Low Voltage XTAL1[*4] Input High Voltage
0 2.4
0.8 VDD +0.2 VDD +0.2 VDD +0.2 0.45 0.45 8 14 -180 -14
V V V V V V mA mA V V A mA
VDD = 4.5V VD D = 5.5V VDD = 5.5V VDD = 5.5V VDD = 4.5V IOL = +2 mA VDD = 4.5V IOL = +4 mA VDD = 4.5V VOL = 0.45V VDD=4.5V VOL = 0.45V VDD = 4.5V IOH = -100 A VDD = 4.5V IOH = -400 A VDD = 4.5V VOH = 2.4V VDD =4.5V VOH = 2.4V
P0, P1, P2, P3, P4, EA Input High Voltage RST Input High Voltage XTAL1[*4] Output Low Voltage P1, P2, P3, P4 Output Low Voltage P0, ALE, PSEN Sink current P1, P3, P4 Sink current P0, P2, ALE, PSEN Output High Voltage P1, P2, P3, P4 Output High Voltage P0, ALE, PSEN Source current P1, P2, P3, P4 Source current P0, P2, ALE, PSEN -10
[*3] [*3]
3.5 3.5 4 10 2.4 2.4 -120
*1. RST pin is a Schmitt trigger input. *2. P0, ALE and PSEN are tested in the external access mode.
*3. XTAL1 is a CMOS input. *4. Pins of P1, P2, P3, P4 can source a transition current when they are being externally driven from 1 to 0.
- 28 -
W78E365/W78E365A
7.3 A.C. Characteristics
The AC specifications are a function of the particular process used to manufacture the part, the ratings of the I/O buffers, the capacitive load, and the internal routing capacitance. Most of the specifications can be expressed in terms of multiple input clock periods (TCP), and actual parts will usually experience less than a 20 nS variation. Clock Input Waveform
XTAL1
T CH F OP, TCP T CL
PARAMETER
SYMBOL
MIN.
TYP.
MAX.
UNIT
NOTES
Operating Speed Clock Period Clock High Clock Low
FOP TCP TCH TCL
0 25 20 20
-
40 -
MHz nS nS nS
1 2 3 3
Notes: 1. The clock may be stopped indefinitely in either state. 2. The TCP specification is used as a reference in other specifications. 3. There are no duty cycle requirements on the XTAL1 input.
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Publication Release Date: January 10, 2007 Revision A9
W78E365/W78E365A
8. TIMING WAVEFORMS
8.1 Program Fetch Cycle
S1 XTAL1
S2
S3
S4
S5
S6
S1
S2
S3
S4
S5
S6
TALW ALE TAPL PSEN TPSW TAAS PORT 2 TAAH PORT 0 Code A0-A7 Data A0-A7 Code A0-A7 Data A0-A7 TPDA TPDH, TPDZ
PARAMETER
SYMBOL
MIN.
TYP.
MAX.
UNIT
NOTES
Address Valid to ALE Low Address Hold from ALE Low ALE Low to PSEN Low
TAAS TAAH TAPL TPDA TPDH TPDZ TALW TPSW
1 TCP- 1 TCP- 1 TCP- 0 0 2 TCP- 3 TCP-
2 TCP 3 TCP
2 TCP 1 TCP 1 TCP -
nS nS nS nS nS nS nS nS
4 1, 4 4 2 3
PSEN Low to Data Valid
Data Hold after PSEN High Data Float after PSEN High ALE Pulse Width
PSEN Pulse Width
4 4
Notes: 1. P0.0-P0.7, P2.0-P2.7 remain stable throughout entire memory cycle. 2. Memory access time is 3 TCP.
3. Data have been latched internally prior to PSEN going high. 4. "" (due to buffer driving delay and wire loading) is 20 nS.
- 30 -
W78E365/W78E365A
8.2 Data Read Cycle
S4 XTAL1 ALE PSEN PORT 2
S5
S6
S1
S2
S3
S4
S5
S6
S1
S2
S3
A8-A15 A0-A7 DATA TDAR TDDA
PORT 0 TDDH, TDDZ RD TDRD
PARAMETER
SYMBOL
MIN.
TYP.
MAX.
UNIT
NOTES
ALE Low to RD Low
RD Low to Data Valid
TDAR TDDA TDDH TDDZ TDRD
3 TCP- 0 0 6 TCP-
6 TCP
3 TCP+ 4 TCP 2 TCP 2 TCP -
nS nS nS nS nS
1, 2 1
Data Hold from RD High Data Float from RD High
RD Pulse Width
2
Notes: 1. Data memory access time is 8 TCP. 2. "" (due to buffer driving delay and wire loading) is 20 nS.
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Publication Release Date: January 10, 2007 Revision A9
W78E365/W78E365A
8.3 Data Write Cycle
S4 XTAL1 ALE PSEN PORT 2 PORT 0 WR
S5
S6
S1
S2
S3
S4
S5
S6
S1
S2
S3
A8-A15 A0-A7 DATA OUT
TDAD
T DWD
T DAW
T DWR
PARAMETER
SYMBOL
MIN.
TYP.
MAX.
UNIT
ALE Low to WR Low Data Valid to WR Low Data Hold from WR High
WR Pulse Width
TDAW TDAD TDWD TDWR
3 TCP- 1 TCP- 1 TCP- 6 TCP-
6 TCP
3 TCP+ -
nS nS nS nS
Note: "" (due to buffer driving delay and wire loading) is 20 nS.
- 32 -
W78E365/W78E365A
8.4 Port Access Cycle
S5 XTAL1
S6
S1
ALE TPDS PORT INPUT SAMPLE TPDH T PDA DATA OUT
PARAMETER
SYMBOL
MIN.
TYP.
MAX.
UNIT
Port Input Setup to ALE Low Port Input Hold from ALE Low Port Output to ALE
TPDS TPDH TPDA
1 TCP 0 1 TCP
-
-
nS nS nS
Note: Ports are read during S5P2, and output data becomes available at the end of S6P2. The timing data are referenced to ALE, since it provides a convenient reference.
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Publication Release Date: January 10, 2007 Revision A9
W78E365/W78E365A
9. TYPICAL APPLICATION CIRCUIT
9.1 External Program Memory and Crystal
V DD
31 19 10 u R
CRYSTAL
EA XTAL1 XTAL2 RST INT0 INT1 T0 T1 P1.0 P1.1 P1.2 P1.3 P1.4 P1.5 P1.6 P1.7
18 9
8.2 K C1 C2
P0.0 P0.1 P0.2 P0.3 P0.4 P0.5 P0.6 P0.7 P2.0 P2.1 P2.2 P2.3 P2.4 P2.5 P2.6 P2.7 RD WR PSEN ALE TXD RXD
39 AD0 38 AD1 37 AD2 36 AD3 35 AD4 34 AD5 33 AD6 32 AD7 21 22 23 24 25 26 27 28 17 16 29 30 11 10 A8 A9 A10 A11 A12 A13 A14 A15
AD0 AD1 AD2 AD3 AD4 AD5 AD6 AD7 GND
3 4 7 8 13 14 17 18 1 11
D0 D1 D2 D3 D4 D5 D6 D7 OC G
Q0 Q1 Q2 Q3 Q4 Q5 Q6 Q7
2 5 6 9 12 15 16 19
A0 A1 A2 A3 A4 A5 A6 A7
12 13 14 15 1 2 3 4 5 6 7 8
74LS373
A0 10 A1 9 A2 8 A3 7 A4 6 A5 5 A6 4 A7 3 A8 25 A9 24 A10 21 A11 23 A12 2 A13 26 A14 27 A15 1 GND 20 22
A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 A11 A12 A13 A14 A15 CE OE 27512
O0 O1 O2 O3 O4 O5 O6 O7
11 12 13 15 16 17 18 19
AD0 AD1 AD2 AD3 AD4 AD5 AD6 AD7
W78E365/W78E365A
Figure A
CRYSTAL
C1
C2
R
6 MHz 16 MHz 24 MHz 32 MHz 40 MHz
47P 30P 15P 10P 5P
47P 30P 15P 10P 5P
6.8K 4.7K
Above table shows the reference values for crystal applications.
Notes:
1. C1, C2, R components refer to Figure A 2. Crystal layout must get close to XTAL1 and XTAL2 pins on user's application board. Typical Application Circuit, continued
- 34 -
W78E365/W78E365A
9.2 Expanded External Data Memory and Oscillator
VDD VDD 31 19 10 u OSCILLATOR 18 8.2 K 9 12 13 14 15 1 2 3 4 5 6 7 8 EA XTAL1 XTAL2 RST INT0 INT1 T0 T1 P1.0 P1.1 P1.2 P1.3 P1.4 P1.5 P1.6 P1.7 P0.0 P0.1 P0.2 P0.3 P0.4 P0.5 P0.6 P0.7 P2.0 P2.1 P2.2 P2.3 P2.4 P2.5 P2.6 P2.7 RD WR PSEN ALE TXD RXD 39 38 37 36 35 34 33 32 21 22 23 24 25 26 27 28 17 16 29 30 11 10 AD0 AD1 AD2 AD3 AD4 AD5 AD6 AD7 A8 A9 A10 A11 A12 A13 A14 AD0 AD1 AD2 AD3 AD4 AD5 AD6 AD7 GND 3 4 7 8 13 14 17 18 1 11 D0 D1 D2 D3 D4 D5 D6 D7 OC G 74LS373 Q0 Q1 Q2 Q3 Q4 Q5 Q6 Q7 2 5 6 9 12 15 16 19 A0 A1 A2 A3 A4 A5 A6 A7 A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 A11 A12 A13 A14 GND 10 9 8 7 6 5 4 3 25 24 21 23 2 26 1 20 22 27 A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 A11 A12 A13 A14 CE OE WR 20256 D0 D1 D2 D3 D4 D5 D6 D7 11 12 13 15 16 17 18 19 AD0 AD1 AD2 AD3 AD4 AD5 AD6 AD7
W78E365/W78E365A
Figure B
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Publication Release Date: January 10, 2007 Revision A9
W78E365/W78E365A
10. PACKAGE DIMENSIONS
10.1 40-pin DIP
Symbol
Dimension in inch Dimension in mm Min. Nom. Max. Min. Nom. Max.
0.210 0.010 0.150 0.016 0.048 0.008 0.155 0.018 0.050 0.010 2.055 0.590 0.540 0.090 0.120 0 0.630 0.650 0.600 0.545 0.100 0.130 0.160 0.022 0.054 0.014 2.070 0.610 14.986 0.550 0.110 0.140 15 0.670 0.090 13.72 2.286 3.048 0 16.00 16.51 0.254 3.81 0.406 1.219 0.203 3.937 0.457 1.27 0.254 52.20 15.24 13.84 2.54 3.302 4.064 0.559 1.372 0.356 52.58 15.494 13.97 2.794 3.556 15 17.01 2.286 5.334
D 40 21
E1
A A1 A2 B B1 c D E E1 e1 L
a
1 S
20 E c
eA S
Notes:
A A2
A1
Base Plane Seating Plane
L B B1
e1
a
eA
1. Dimension D Max. & S include mold flash or tie bar burrs. 2. Dimension E1 does not include interlead flash. 3. Dimension D & E1 include mold mismatch and . are determined at the mold parting line. 4. Dimension B1 does not include dambar protrusion/intrusion. 5. Controlling dimension: Inches. 6. General appearance spec. should be based on final visual inspection spec.
10.2 44-pin PLCC
HD D
6 1 44 40
Symbol
7 39
Dimension in inch Min. Nom. Max.
0.185 0.020 0.145 0.026 0.016 0.008 0.648 0.648 0.150 0.028 0.018 0.010 0.653 0.653 0.155 0.032 0.022 0.014 0.658 0.658
Dimension in mm Min. Nom. Max.
4.699 0.508 3.683 0.66 0.406 0.203 16.46 16.46 3.81 0.711 0.457 0.254 16.59 16.59 3.937 0.813 0.559 0.356 16.71 16.71
E
HE
GE
17
29
18
28
c
A A1 A2 b1 b c D E e GD GE HD HE L y
Notes:
0.050 0.590 0.590 0.680 0.680 0.090
BSC 0.630 0.630 0.700 0.700 0.110 0.004
1.27 14.99 14.99 17.27 17.27 2.296
BSC 16.00 16.00 17.78 17.78 2.794 0.10
0.610 0.610 0.690 0.690 0.100
15.49 15.49 17.53 17.53 2.54
L A2 A
e
Seating Plane GD
b b1
A1 y
1. Dimension D & E do not include interlead flash. 2. Dimension b1 does not include dambar protrusion/intrusion. 3. Controlling dimension: Inches 4. General appearance spec. should be based on final visual inspection spec.
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W78E365/W78E365A
10.3 44-pin PQFP
HD D
Dimension in inch
Dimension in mm
Symbol
44 34
Min. Nom. Max.
--0.002 0.075 0.01 0.004 0.390 0.390 0.025 0.510 0.510 0.025 0.051 --0.01 0.081 0.014 0.006 0.394 0.394 0.031 0.520 0.520 0.031 0.063 --0.02 0.087 0.018 0.010 0.398 0.398 0.036 0.530 0.530 0.037 0.075 0.003 0 7
Min. Nom.
--0.05 1.90 0.25 0.101 9.9 9.9 0.635 12.95 12.95 0.65 1.295 --0.25 2.05 0.35 0.152 10.00 10.00 0.80 13.2 13.2 0.8 1.6
Max.
--0.5 2.20 0.45 0.254 10.1 10.1 0.952 13.45 13.45 0.95 1.905 0.08
1
33
E HE
11
12
e
b
22
A A1 A2 b c D E e HD HE L L1 y
Notes:
c
0
7
A2 A A1 L L1 Detail F
Seating Plane
See Detail F
y
1. Dimension D & E do not include interlead flash. 2. Dimension b does not include dambar protrusion/intrusion. 3. Controlling dimension: Millimeter 4. General appearance spec. should be based on final visual inspection spec.
10.4 48-pin LQFP
HD D
36 25
Symbol
Dimension in mm Min. Nom.
--0.05 1.35 0.17 0.09 ----1.40 0.20 --7.00 7.00 0.50 9.00 9.00 0.45 0.60 1.00 --0 0.08 3.5 --7 0.75
Max.
1.60 0.15 1.45 0.27 0.20
37
24
E
HE
48
13
1
e
b
12
A A1 A2 b c D E e HD HE L L1 y 0
Notes:
c
A2
A
Seating Plane
See Detail F
A1 y
L L1 Detail F
1. Dimensions D & E do not include interlead flash. 2. Dimension b does not include dambar protrusion/intrusion. 3. Controlling dimension: Millimeters 4. General appearance spec. should be based on final visual inspection spec.
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Publication Release Date: January 10, 2007 Revision A9
W78E365/W78E365A
11. APPLICATION NOTE
11.1 In-system Programming Software Examples
This application note illustrates the in-system programmability of the Winbond W78E365 ROM microcontroller. In this example, microcontroller will boot from 64KB APROM bank and waiting for a key to enter in-system programming mode for re-programming the contents of 64KB APROM. While entering in-system programming mode, microcontroller executes the loader program in 4KB LDROM bank. The loader program erases the 64KB APROM then reads the new code data from external SRAM buffer (or through other interfaces) to update the 64KB APROM. Example 1: ;******************************************************************************************************************* ;* Example of 64K APROM program: Program will scan the P1.0. if P1.0 = 0, enters in-system ;* programming mode for updating the content of APROM code else executes the current ROM code. ;* XTAL = 16 MHz ;*******************************************************************************************************************
.chip 8052 .RAMCHK OFF .symbols CHPCON CHPENR SFRAL SFRAH SFRFD SFRCN EQU EQU EQU EQU EQU EQU BFH F6H C4H C5H C6H C7H
ORG 0H LJMP 100H ; JUMP TO MAIN PROGRAM ;************************************************************************ ;* TIMER0 SERVICE VECTOR ORG = 000BH ;************************************************************************ ORG 00BH CLR TR0 ; TR0 = 0, STOP TIMER0 MOV TL0, R6 MOV TH0, R7 RETI ;************************************************************************ ;* 64K APROM MAIN PROGRAM ;************************************************************************ ORG 100H MAIN_64K: MOV A,P1 ; SCAN P1.0 ANL A, #01H CJNE A, #01H,PROGRAM_64K ; IF P1.0 = 0, ENTER IN-SYSTEM PROGRAMMING MODE JMP NORMAL_MODE PROGRAM_64K: MOV CHPENR, #87H MOV CHPENR, #59H MOV CHPCON, #03H MOV TCON, #00H
; CHPENR = 87H, CHPCON REGISTER WRTE ENABLE ; CHPENR = 59H, CHPCON REGISTER WRITE ENABLE ; CHPCON = 03H, ENTER IN-SYSTEM PROGRAMMING MODE ; TR = 0 TIMER0 STOP
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W78E365/W78E365A
MOV IP, #00H MOV IE, #82H MOV R6, #F0H MOV R7, #FFH MOV TL0, R6 MOV TH0, R7 MOV TMOD, #01H MOV TCON, #10H MOV PCON, #01H ; IP = 00H ; TIMER0 INTERRUPT ENABLE FOR WAKE-UP FROM IDLE MODE ; TL0 = F0H ; TH0 = FFH
; TMOD = 01H, SET TIMER0 A 16-BIT TIMER ; TCON = 10H, TR0 = 1,GO ; ENTER IDLE MODE FOR LAUNCHING THE IN-SYSTEM ; PROGRAMMING
;******************************************************************************** ;* Normal mode 64KB APROM program: depending user's application ;******************************************************************************** NORMAL_MODE: . . . . ; User's application program
Example 2:
;****************************************************************************************************************************** Example of 4 KB LDROM program: This loader program will erase the 64KB APROM first, then reads the new ;* code from external SRAM and program them into 32 KB APROM bank. XTAL = 16 MHz ;***************************************************************************************************************************** .chip 8052 .RAMCHK OFF .symbols CHPCON CHPENR SFRAL SFRAH SFRFD SFRCN ORG LJMP EQU EQU EQU EQU EQU EQU 000H 100H BFH F6H C4H C5H C6H C7H
; JUMP TO MAIN PROGRAM
;************************************************************************ ;* 1. TIMER0 SERVICE VECTOR ORG = 0BH ;************************************************************************ ORG 000BH CLR TR0 ; TR0 = 0, STOP TIMER0 MOV TL0, R6 MOV TH0, R7 RETI
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Publication Release Date: January 10, 2007 Revision A9
W78E365/W78E365A
;************************************************************************ ;* 4KB LDROM MAIN PROGRAM ;************************************************************************ ORG 100H MAIN_4K: MOV SP, #C0H MOV CHPENR, #87H ; CHPENR = 87H, CHPCON WRITE ENABLE. MOV CHPENR, #59H ; CHPENR = 59H, CHPCON WRITE ENABLE. MOV CHPCON, #03H ; CHPCON = 03H, ENABLE IN-SYSTEM PROGRAMMING. MOV CHPENR, #00H ; DISABLE CHPCON WRITE ATTRIBUTE MOV TCON, #00H MOV TMOD, #01H MOV IP, #00H MOV IE, #82H MOV R6, #F0H MOV R7, #FFH MOV TL0, R6 MOV TH0, R7 MOV TCON, #10H MOV PCON, #01H UPDATE_64K: MOV TCON, #00H MOV IP, #00H MOV IE, #82H MOV TMOD, #01H MOV R6, #E0H MOV R7, #B1H MOV TL0, R6 MOV TH0, R7 ERASE_P_4K: MOV SFRCN, #22H MOV TCON, #10H MOV PCON, #01H ; TCON = 00H, TR = 0 TIMER0 STOP ; TMOD = 01H, SET TIMER0 A 16BIT TIMER ; IP = 00H ; IE = 82H, TIMER0 INTERRUPT ENABLED
; TCON = 10H, TR0 = 1, GO ; ENTER IDLE MODE
; TCON = 00H, TR = 0 TIM0 STOP ; IP = 00H ; IE = 82H, TIMER0 INTERRUPT ENABLED ; TMOD = 01H, MODE1 ; SET WAKE-UP TIME FOR ERASE OPERATION, ABOUT 15 mS. DEPENDING ; ON USER'S SYSTEM CLOCK RATE.
; SFRCN(C7H) = 22H ERASE 64K ; TCON = 10H, TR0 = 1,GO ; ENTER IDLE MODE (FOR ERASE OPERATION)
;********************************************************************* ;* BLANK CHECK ;********************************************************************* MOV SFRCN, #0H ; READ 64KB APROM MODE MOV SFRAH, #0H ; START ADDRESS = 0H MOV SFRAL, #0H MOV R6, #FEH ; SET TIMER FOR READ OPERATION, ABOUT 1.5 S. MOV R7, #FFH MOV TL0, R6 MOV TH0, R7 BLANK_CHECK_LOOP: SETB TR0 ; ENABLE TIMER 0 MOV PCON, #01H ; ENTER IDLE MODE MOV A, SFRFD ; READ ONE BYTE CJNE A, #FFH, BLANK_CHECK_ERROR INC SFRAL ; NEXT ADDRESS
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W78E365/W78E365A
MOV A, SFRAL JNZ BLANK_CHECK_LOOP INC SFRAH MOV A, SFRAH CJNE A, #80H, BLANK_CHECK_LOOP ; END ADDRESS = 7FFFH JMP PROGRAM_64KROM BLANK_CHECK_ERROR: MOV P1, #F0H MOV P3, #F0H JMP $ ;******************************************************************************* ;* RE-PROGRAMMING 64KB APROM BANK ;******************************************************************************* PROGRAM_64KROM: MOV DPTR, #0H ; THE ADDRESS OF NEW ROM CODE MOV R2, #00H ; TARGET LOW BYTE ADDRESS MOV R1, #00H ; TARGET HIGH BYTE ADDRESS MOV DPTR, #0H ; EXTERNAL SRAM BUFFER ADDRESS MOV SFRAH, R1 ; SFRAH, TARGET HIGH ADDRESS MOV SFRCN, #21H ; SFRCN(C7H) = 21 (PROGRAM 64K) MOV R6, #BEH ; SET TIMER FOR PROGRAMMING, ABOUT 50 S. MOV R7, #FFH MOV TL0, R6 MOV TH0, R7 PROG_D_64K: MOV SFRAL, R2 MOVX A, @DPTR ; SFRAL(C4H) = LOW BYTE ADDRESS ; READ DATA FROM EXTERNAL SRAM BUFFER. BY ACCORDING USER? ; CIRCUIT, USER MUST MODIFY THIS INSTRUCTION TO FETCH CODE ; SFRFD(C6H) = DATA IN ; TCON = 10H, TR0 = 1,GO ; ENTER IDLE MODE (PRORGAMMING)
MOV SFRFD, A MOV TCON, #10H MOV PCON, #01H INC DPTR INC R2 CJNE R2, #0H, PROG_D_64K INC R1 MOV SFRAH, R1 CJNE R1, #80H, PROG_D_64K
;***************************************************************************** ; * VERIFY 64KB APROM BANK ;***************************************************************************** MOV R4, #03H ; ERROR COUNTER MOV R6, #FEH ; SET TIMER FOR READ VERIFY, ABOUT 1.5 S. MOV R7, #FFH MOV TL0, R6 MOV TH0, R7 MOV DPTR, #0H ; The start address of sample code MOV R2, #0H ; Target low byte address MOV R1, #0H ; Target high byte address MOV SFRAH, R1 ; SFRAH, Target high address MOV SFRCN, #00H ; SFRCN = 00 (Read ROM CODE)
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Publication Release Date: January 10, 2007 Revision A9
W78E365/W78E365A
READ_VERIFY_64K: MOV SFRAL, R2 ; SFRAL(C4H) = LOW ADDRESS MOV TCON, #10H ; TCON = 10H, TR0 = 1,GO MOV PCON, #01H INC R2 MOVX A, @DPTR INC DPTR CJNE A, SFRFD, ERROR_64K CJNE R2, #0H, READ_VERIFY_64K INC R1 MOV SFRAH, R1 CJNE R1, #80H, READ_VERIFY_64K ;****************************************************************************** ;* PROGRAMMING COMPLETLY, SOFTWARE RESET CPU ;****************************************************************************** MOV CHPENR, #87H ; CHPENR = 87H MOV CHPENR, #59H ; CHPENR = 59H MOV CHPCON, #83H ; CHPCON = 83H, SOFTWARE RESET. ERROR_64K: DJNZ R4, UPDATE_64K . . . .
; IF ERROR OCCURS, REPEAT 3 TIMES. ; IN-SYSTEM PROGRAMMING FAIL, USER'S PROCESS TO DEAL WITH IT.
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W78E365/W78E365A
12. REVISION HISTORY
VERSION DATE PAGE DESCRIPTION
A1 A2 A3 A4 A5 A6 A7 A8 A9
May, 2003 August, 2004 Sep. 14, 2004 Dec. 23, 2004 April 20, 2005 June 22, 2005 Aug. 25, 2005 Dec 4, 2006 January 10, 2007
32 2 2, 15 41 3 33 3, 5 3 3 4 37
Initial Issued Revise title of 9.1 Remove P4.4 ~ P4.7 Add PWM in feature list and modify PWM block diagram Add Important Notice Add lead free(RoHS) part number Add 32M/40Mhz items in the table Add Port 0 pull-up resisters information Remove all Leaded package parts Add 48-pin LQFP part. Add 48-pin LQFP package Add 48-pin LQFP package dimension Important Notice
Winbond products are not designed, intended, authorized or warranted for use as components in systems or equipment intended for surgical implantation, atomic energy control instruments, airplane or spaceship instruments, transportation instruments, traffic signal instruments, combustion control instruments, or for other applications intended to support or sustain life. Further more, Winbond products are not intended for applications wherein failure of Winbond products could result or lead to a situation wherein personal injury, death or severe property or environmental damage could occur. Winbond customers using or selling these products for use in such applications do so at their own risk and agree to fully indemnify Winbond for any damages resulting from such improper use or sales.
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Publication Release Date: January 10, 2007 Revision A9

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